(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to active pixel sensor technology.
(2) Description of Prior Art
CMOS image sensors (CIS) are widely used in a large variety of products. Examples of these products are smart phones, screen phones, digital cameras, PC cameras, surveillance equipment, digital camcorders and toys. It is expected that utilization of CIS will be even more extensive in the future. For the increased utilization of CIS products it is important that there is a concurrent increase in the quality of the CIS digital picture. A high density of pixels is required for improved picture quality. Higher pixel density implies smaller pixel area, but, in the absence of improved efficiency, smaller pixel area results in a lower efficiency. Thus just scaling down a conventional CIS pixel will result in a smaller pixel of reduced sensitivity. It is an objective of the invention to provide a novel photodiode structure that will increase the CIS pixel sensitivity to the extent that even with an extreme reduction in size the pixel sensitivity will be as good or better than conventional CIS pixels.
A popular conventional active pixel based on CMOS, shown in FIG. 1, contains one photo-diode and three n-channel MOS transistors (for reset, source follower, and row access). The “reset transistor”, 10, is used for resetting the potential of the floating-node of photo-diode 12 to Vcc. The floating-node of the photo-diode is connected to the gate of “source follower” 14, where its conductance is modulated by the floating-node potential. After reset operation, the potential of photo-diode is modulated (decreasing) by accumulating electrons generated by image light (or photons) during the “image integration” period. After turning on the row access transistor, 16, Vo is read out (one VT below the floating-node potential) as the output of the image signal. The output is essentially linear with the photo-signal (i.e. floating-node potential), which is proportional to the number of electrons generated by the image light. The number of electrons generated by the image light is in turn proportional to the area of the photodiode junction. A higher sensitivity is therefor achieved for larger area photodiodes. Consequently the photodiode occupies the largest fraction of the pixel area. This is seen in FIG. 2, which shows the layout of a typical CIS pixel. The photodiode, 12, clearly occupies the majority of the pixel area. In FIG. 2, region 34 is the active pixel area except for the photodiode A traditional structure for a CIS photodiode is shown in FIG. 3, where the upper n-type region, 18, is an n-well formed in a p-type substrate, 20. A depletion region forms about an area, A0, i.e., about each of the surfaces of the n-well except for the upper surface. The photo-response is thus proportional to the area A0=1w+2h(1+w), where 1 is the length, 24, w is the width, 26, and h is the height, 22, of the n-well.
Pinned photodiodes are used by Lee et al., U.S. Pat. No. 6,027,955, and Lee et al., U.S. Pat. No. 6,051,447, in image sensors to increase the fill factor of the photodetector. Riglet et al., U.S. Pat. No. 4,904,607, disclose a method of manufacturing an infrared detector having a buried PIN photodiode. A method of forming an image sensor and a CMOS logic circuit device is shown in U.S. Pat. No. 6,194,258 to Wuu. The method shows how to prevent the formation of metal silicide on the photodiode element.